1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to a method of manufacturing a semiconductor device, in which a gate electrode is formed in a T-shape in order to increase the size of a top surface of the gate electrode, thereby providing a stable silicide forming condition and preventing contact misalignment.
2. Background of the Related Art
With advancement in semiconductor techniques, high-speed and high-integration of semiconductor devices are rapidly progressed, and accordingly, requirements on scale down of patterns and high-precision of pattern sizes are gradually increased.
A large progress is accomplished in reduction of gate line width, copper wiring process, and the like in order to satisfy such conditions. In the case of gate/source/drain and a contact hole, high-integration and high-performance are accomplished using a technique of forming BorderlessContact.
Presently, the gate electrode of a semiconductor device is formed in a straight form where mainly gate oxide and polysilicon films are stacked, and a method of etching the polysilicon film using a mask pattern is used to form the gate electrode.
However, in such a method described above, it is difficult to form a metal silicide film on the top of the gate electrode since width of the gate electrode is decreased as the device is highly integrated more and more, and a resistance value of the metal silicide film is high and unstable.
In addition, generation of misalignment is gradually increased when a contact is formed, and it is difficult to for a gate electrode due to limit in a process.
Furthermore, since non-uniformity in thickness of inter-layer dielectric is increased, there is a problem of excessive over-etching when a contact is etched. Therefore, there is a problem in that the gate electrode is damaged, and silicon in the source/drain regions is etched, thereby deepening a junction region.
In order to improve such problems, a technique of forming a gate in a T-shape is disclosed in Korean Patent Application No. 2001-0037228.
However, in the technique, a T-shape gate electrode is formed by defining a gate region using photo-resist, depositing an insulation film on the other region, removing the photo-resist defining the gate region, depositing a gate material, and performing a post-process.
However, in this technique, a gate region is defined using photo-resist, and an insulation film is deposited thereon. At this point, there is a problem in that since the photo-resist cannot endure the insulation film deposition process of high temperature, a photo-resist pattern for defining the gate region is damaged.